As display screens are being developed constantly, there is an increasing demand from consumers for the stability of the display screens. The stability of the display screens is significantly dependent on gate driver circuits, and shift registers constituting the gate driver circuits.
At present, a shift register is generally structured in 5T2C (that is, it includes five switching transistors and two capacitors). As illustrated in FIG. 1 which is a schematic structural diagram of a shift register in the prior art, all of the first switching transistor M1 to the fifth switching transistor M5 are P-type thin film transistors. As illustrated in FIG. 2 which is a scheme timing diagram thereof, when a low-level signal is output at an output signal terminal OUT, the third switching transistor M3 is turned-on due to the low-level signal output by the output signal terminal OUT, and at this time, a high-level signal output at a first reference signal terminal VGH is transmitted to a first node N1 due to the third switching transistor M3 which is turned-on. The fifth switching transistor M5 is turned-off due to the high-level signal at the first node N1. If there is not a low-level signal to be written in a timely manner into the first node N1 being persistent in the high-level state, then there will be an abnormal output at the output signal terminal OUT, thus resulting in a risk of contention in the scheme, and making the shift register instable.
In view of this, there is highly desirable at present to provide such a stable shift register and gate driver circuit that can enable a normal output at an output terminal thereof while guaranteeing the stability thereof.